Low-Power Logic Circuit and SRAM Cell Applications With Silicon on Depletion Layer MOS (SODEL CMOS) Technology

Low-Power Logic Circuit and SRAM Cell

Applications With Silicon on Depletion Layer MOS

(SODEL CMOS) Technology

(Satoshi Inaba, Member, IEEE, Hajime Nagano, Kiyotaka Miyano, Ichiro Mizushima, Yasunori Okayama, Takahiro Nakauchi, Kazunari Ishimaru, Senior Member, IEEE, and Hidemi Ishiuchi, Member, IEEE)

                     By:

                     Garima Verma

                     PGDIE-42

                     A-31

Abstract:

In this paper, the switching performance of Silicon on Depletion Layer CMOS (SODEL CMOS) [1] is investigated with a view to realizing high-speed and low-power CMOS applications. Thanks to smaller parasitic capacitance, the propagation delay time (Tpd) in SODEL CMOS has been improved by up to 25% compared to that of conventional bulk CMOS in five stacked nFET inverters at the same dd. It is also confirmed that about 30% better power-delay product can be realized at the same pd with reduced V_dd in SODEL CMOS. In SRAM cell applications, SODEL CMOS shows high Static Noise Margin (SNM) of 95 mV at dd = 06 V. Smaller bitline delay is expected and confirmed in SODddEL CMOS SRAM by SPICE simulations. Latch-up immunity for -particle irradiation in SODEL CMOS was also found to be comparable to that of conventional bulk CMOS. Therefore, SODEL CMOS device and circuit technology is expected to provide a better solution for lowpower system-on-a-chip (SoC).

Summary:

RECENTLY,  partially  depleted  SOI  (PD-SOI)  CMOS devices have emerged as one of the promising solutions for high-performance CMOS applications. It is offering many advantages  over  conventional  bulk  CMOS,  such  as  larger   due to the floating body effect (FBE), smaller junction capacitance  (Cj)  and  less  body  effect  [2].  However,  there are many disadvantages to be overcome concerning PD-SOI CMOS devices, such as the history effect, wafer quality and cost, gate oxide integrity, self-heating, and additional option of body contact to fix the body potential. If desirable SOI CMOS device characteristics were realized using conventional bulk CMOS technology, a better solution would be available for high-performance and low-power CMOS, and especially so for system-on-a-chip (SoC) applications.

The new MOSFET device concept of Silicon On DEple- tion Layer FET (SODEL FET) has been proposed to achieve high-performance in future CMOS applications [1]. For ex- ample, SODEL FET on a bulk silicon wafer has an artificial depletion layer which works as an insulator like a buried oxide (BOX) in SOI MOSFET. The artificial depletion layer is made by junction beneath a channel region in SODEL nFET. In the case of SODEL pFET, the artificial depletion layer is formed by junction beneath the channel region. In contrast to PD-SOI devices, the holes generated by impact ionization can be swept away from channel region to substrate, and therefore, the kink effect or the history effect will be suppressed in SODEL FET [1].

II. Device Structure and Fabrication Of SODEL CMOS

SODEL CMOS is fabricated with bulk CMOS compatible process; however, fabrication of the depletion layer region requires the silicon epitaxy technique in the channel region to optimize the impurity profiles, and also requires two additional mask and ion implant processes in both nFET and pFET. By forming stacked region beneath the channel region, the depletion layer is extended to below the source/drain region. Therefore, smaller C_j                fF m  and smaller body effect V have been achieved in SODEL nFET. In a previous study [1], the minimum gate length of normally operating SODEL FET was about 70–90 nm, because the impurity profiles in channel and source/drain were not optimized.

III. Switching Performance in SODEL CMOS Devices

Propagation delay time  T_pd in a CMOS inverter is a key parameter for the prediction of total LSI performance. Though, T_pd in the latest logic circuit is influenced by large interconnect capacitance, the contribution of the parasitic effect also cannot be neglected in of recent CMOS

devices. Thanks to smaller Cj in S/D diffusion region and smaller body effect, faster switching is expected in SODEL CMOS logic circuit. In fact, difference between SODEL CMOS and conventional bulk CMOS has been observed in our standard inverter case (F/O=1 , un- loaded), under the condition of the same drain currents. The difference of should be caused by differences of Cj and physical gate length in both devices. In this experiment, the average drawn gate length would be about 70 nm and was slightly smaller in SODEL CMOS case than that in conventional CMOS case in referred ring oscillator hardwares. The difference is due to the wafer to wafer variation of average drawn gate lengths in gate stack formation process.

IV. Spice Simulations O SODEL CMOS for Static And Dynamic Logic Circuits

Next, the advantage of SODEL CMOS has been investigated by SPICE simulations both for static and dynamic logic circuits The device parameters of SODEL CMOS for SPICE simulation with BSIM3v3 model were extracted by a commercially avail- able tool. At first, the extracted device parameters in SPICE simulations were verified by the reproduction of the experimental  T_pd’s in standard inverter. Then, T_pd of multi-input NAND logic gate were simulated. From the simulation results, it has been found that the delay time improvement will be about 16% in bottom switching and 23% in top switching for 4-input NAND logic gate Larger improvement in top switching than in bottom switching may also be due to smaller body effect and smaller Cj in pFETs and top nFET as discussed in the previous section. These results suggest that SODEL CMOS provides higher speed or lower power in stacked logic gate circuits, such as A/D converters, adders and multipliers with pass-transistor logic.

V.  SRAM Application of SODEL CMOS Technology

To confirm the applicability of SODEL CMOS to real LSI, 1 Mbit SRAM Array Diagnostic Monitor (ADM) has been fabricated with 90-nm CMOS technology. Fig. 12 shows the chip micrograph of 1 Mbit SODEL CMOS SRAM ADM with Cu metal process. It is composed of 8 blocks of 128 K SRAM cell arrays. Measured function bit rate suddenly fell at suddenly fell at V due to high  in support devices of peripheral circuit. However, since    variation of fail bit was very small in V_dd V, we think normal SRAM operation should be extended to V_dd region down to 0.60 V. These results suggest that SODEL CMOS has sufficient applicability for SRAM cell even at V_dd V. Simulated SRAM cell operation in SODEL CMOS.

VI. Conclusion

It is confirmed for the first time that SODEL CMOS technology can realize higher AC performance, extending to the high-speed or low-power operation regime. Propagation delay time and power-delay product in SODEL CMOS will be about 20% smaller than those in conventional bulk CMOS. The performance improvement is due to smaller Cj and smaller body effect, like in PD-SOI CMOS. 1 Mbit SRAM ADMs were also fabricated by using SODEL CMOS devices with 90-nm node CMOS technology. The measured characteristics and simulation results showed normal behaviour in SODEL CMOS SRAM cell. Therefore, SODEL CMOS technology should provide a potential solution for high-speed, low-power and cost-effective CMOS applications, even in sub-50-nm gate length CMOS generation. SODEL CMOS technology is easily combined with conventional bulk CMOS; therefore, it is also suitable for recent SoC applications, including embedded memory or RF applications

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